VIA C4

Time you got around to sponsoring a child

The VIA C4 range of CPUs is a successor of VIA Technologies' C3. These new processors adopt Pentium 4 Socket 478 and are compatible with all the motherboards having this socket.

The starting frequency is announced as 1 GHz. C4 will have 128 KB of L2 mask. It is composed of 35 million transistors. VIA aims at the market of the entry of range. A version for portable computers is also envisaged.

Just like AMD, the company prefer to name it differently from its frequency. The version 1 GHz will be called "C4 500v" (hypothetically equivalent to Pentium 4 500 MHz in terms of performance).

Here is an explanation of this calculation of this "PR Rating":

1000 MHz X 1.8 = 1800
1800 / 3 = 600
600 X 4,5 = 2700
2700 / 5,4 = 500v

One can thus suppose that version 1500 MHz will be named:

1500 MHz X 1,8 = 2700
2700 / 3 = 900
900 X 4,5 = 4050
4050 / 5,4 = 750v

C4 500v (1000 MHz), 600v (1200 MHz), 650v (1300 MHz) and 700v (1400 MHz) should be launched in the beginning of 2004. Their price has not revealed yet. One criticized more than one once VIA for its sometimes misleading denominations, but one can only congratulate it also bravely to have given up the myth of the gigahertz.

VIA "Esther"

IBM will be producing VIA's "Esther" (Cyrix 4) CPU at East Fishkill. VIA gets access to IBM's copper interconnects, 90nm, and SOI processes. Esther will have SSE2, 128K L1, 256K L2, and should come in around 50mn transistors. It might touch 2Ghz by then. It is about to be introduced in 2Q/2004.

Since the bus agreement with Intel may expire in 2005, VIA may need to prolong it, develop its own bus, or create a chip compatible with non-Intel infrastructure. It might possibly use basic Hypertransport, since it's part of the consortium? It doesn't really need cache coherency, since it's likely going to be single-processor only. It might be able to piggyback off of AMD motherboard infrastructure. But it might have to integrate a memory controller into the CPU core though, unless it wants to run a separate memory controller through Hypertransport.