SSE2
SSE2 is an extension to the IA-32 SIMD instructions, designed by Intel, that extends the earlier SSE set which was in turn an extension of MMX. Support for SSE2 implies support for SSE and MMX.SSE2 adds support for 64-bit double-precision floating point and for 64, 32, 16 and 8-bit integer operations on the eight 128-bit XMM registers first introduced with SSE. SSE2 adds no additional program state to that provided by SSE.
The addition of 128-bit integer SIMD operations allows the programmer to completely avoid the eight 64-bit MMX registers "aliased" on the original IA-32 floating point registers. This permits mixing integer SIMD and scalar floating point operations without the time-consuming mode switching required in MMX and SSE.
Other SSE2 extensions include a set of cache-control instructions intended primarily to minimize cache pollution when processing indefinite streams of information.
SSE2 was first introduced by Intel with the initial version of the Pentium 4. Rival chip-maker AMD later added support for SSE2 in their Opteron and Athlon 64 ranges of CPUs.
SSE2 has itself been extended by SSE3, also known as "Prescott New Instructions", introduced by Intel to the Pentium 4 in early 2004.